SAA7109A Datasheet, PDF (10/197 Pages) NXP Semiconductors – HD-CODEC

Philips Semiconductors
HD-CODEC
Product specification
SAA7108AE; SAA7109AE
SYMBOL
PIN TYPE⁽¹⁾
DESCRIPTION
GREEN_VBS_CVBS C7
O GREEN or VBS or CVBS output
RED_CR_C_CVBS C8
V_DDAe
C9
TEST2
C10
O RED or C_R or C or CVBS output
S 3.3 V analog supply voltage (encoder)
I scan test input 2, do not connect
HPD2
HPD5
IPD1
IPD5
TDOe
C11 I/O MSB − 5 of HPD output bus
C12 I/O MSB − 2 of HPD output bus
C13 O MSB − 6 of IPD output bus
C14 O MSB − 2 of IPD output bus
D1
O test data output for BST (encoder); note 4
RESe
D2
I reset input (encoder); active LOW
TMSe
D3 I/pu test mode select input for BST (encoder); note 4
V_DDIEe
V_SSIe
V_DDXe
VSM
D4
S 3.3 V digital supply voltage for core and peripheral cells (encoder)
D5
S digital ground core (encoder)
D6
S 3.3 V supply voltage for oscillator (encoder)
D7
O vertical synchronization output to VGA monitor (non-interlaced)
HSM_CSYNC
D8
O horizontal synchronization output to VGA monitor (non-interlaced) or
composite sync for RGB-SCART
V_DDAe
V_DDEd
V_DDId
HPD6
IPD2
IPD6
D9
S 3.3 V analog supply voltage (encoder)
D10 S 3.3 V digital supply voltage for peripheral cells (decoder)
D11 S 3.3 V digital supply voltage for core (decoder)
D12 I/O MSB − 1 of HPD output bus
D13 O MSB − 5 of IPD output bus
D14 O MSB − 1 of IPD output bus
TCKe
SCLe
E1 I/pu test clock input for BST (encoder); note 4
E2
I I²C-bus serial clock input (encoder)
HSVGC
E3 I/O horizontal synchronization output to Video Graphics Controller (VGC)
(optional input)
V_SSEe
V_SSId
n.c.
IPD3
E4
S digital ground peripheral cells (encoder)
E11 S digital ground core (decoder)
E12
− not connected
E13 O MSB − 4 of IPD output bus
IPD7
E14 O MSB of IPD output bus
VSVGC
F1 I/O vertical synchronization output to VGC (optional input)
PIXCLKI
F2
I pixel clock input (looped through)
PD3
F3
I MSB − 4 of encoder input bus with C_B-Y-C_R 4 : 2 : 2; see Tables 9 to 15 for
pin assignment
V_DD(DVO)
V_DDId
TVD
F4
S digital supply voltage for DVO cells
F11 S 3.3 V digital supply voltage for core (decoder)
F12 O TV Detector; hot-plug interrupt pin, HIGH if TV is connected
IGPV
F13 O multi-purpose vertical reference output with IPD output bus
IGP0
F14 O general purpose output signal 0 with IPD output bus
2004 Jun 29
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