MFRC53001T Datasheet, PDF (70/116 Pages) NXP Semiconductors – ISO/IEC 14443 A Reader IC

NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
10.5.8.4 Reserved register 3Bh
Table 127. Reserved register (address: 3Bh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
xxxxxxxx
Access
W
Remark: This register is reserved for future use.
10.5.8.5 Reserved register 3Ch
Table 128. Reserved register (address: 3Ch) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
xxxxxxxx
Access
W
Remark: This register is reserved for future use.
10.5.8.6 TestDigiSelect register
Selects digital test mode.
Table 129. TestDigiSelect register (address: 3Dh) reset value: xxxx xxxxb, xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol SignalToMFOUT
TestDigiSignalSel[6:0]
Access
W
W
Table 130. TestDigiSelect register bit descriptions
Bit Symbol
Value Description
7
SignalToMFOUT
1
overrules the MFOUTSelect[2:0] setting and routes the
digital test signal defined with the TestDigiSignalSel[6:0]
bits to pin MFOUT
0
MFOUTSelect[2:0] defines the signal on pin MFOUT
6 to 0 TestDigiSignalSel[6:0] -
selects the digital test signal to be routed to pin MFOUT.
Refer to Section 15.2.3 on page 102 for detailed
information. The following lists the signal names for the
TestDigiSignalSel[6:0] addresses:
F4h
s_data
E4h
s_valid
D4h
s_coll
C4h
s_clock
B5h
rd_sync
A5h
wr_sync
96h
int_clock
83h
BPSK_out
E2h
BPSK_sig
MFRC530_33
Product data sheet
PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 6 July 2010
057433
© NXP B.V. 2010. All rights reserved.
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