MFRC53001T Datasheet, PDF (26/116 Pages) NXP Semiconductors – ISO/IEC 14443 A Reader IC

NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
9.6.3 Standby mode
The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
9.6.4 Automatic receiver power-down
It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD = logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD = logic 0, keeps the receiver continuously powered up.
9.7 StartUp phase
The events executed during the StartUp phase are shown in Figure 9.
states
t_RSTPD
Hard power-
down phase
Fig 9. The StartUp procedure
StartUp phase
t_reset
Reset phase
t_init
Initialising
phase
ready
001aak613
9.7.1 Hard power-down phase
The hard power-down phase is active during the following cases:
• a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when V_DDD or V_DDA is below the relevant analog/digital reset threshold.
• a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100 μs (t_PD ≥ 100 μs). Shorter phases will not
necessarily result in the reset phase (t_reset). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
9.7.2 Reset phase
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see Section 10.5 on page 46).
Remark: When the internal oscillator is used, time (t_osc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by V_DDA and any clock
cycles will not be detected by the internal logic until V_DDA is stable.
MFRC530_33
Product data sheet
PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 6 July 2010
057433
© NXP B.V. 2010. All rights reserved.
26 of 115