MFRC53001T Datasheet, PDF (11/116 Pages) NXP Semiconductors – ISO/IEC 14443 A Reader IC

NXP Semiconductors
MFRC530
ISO/IEC 14443 A Reader IC
Table 8. SPI read address
Address
(MOSI)
Bit 7 Bit 6
(MSB)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)^[1]
byte 0
1
address address address address address address reserved
byte 1 to byte n reserved address address address address address address reserved
byte n + 1
0
0
0
0
0
0
0
0
[1] All reserved bits must be set to logic 0.
9.1.4.2 SPI write data
The structure shown in Table 9 must be used to write data using SPI. It is possible to write
up to n-data bytes. The first byte sent defines both the mode and the address.
Table 9.
MOSI
MISO
SPI write data
Byte 0
address
XX
Byte 1
data 0
XX
Byte 2
data 1
XX
The address byte must meet the following criteria:
... Byte n
... data n − 1
... XX
Byte n + 1
data n
XX
• the MSB of the first byte sets the mode. To write data to the MFRC530, the MSB is set
to logic 0
• bits [6:1] define the address
• the LSB should be set to logic 0.
SPI write mode writes all data to the address defined in byte 0 enabling effective write
cycles to the FIFO buffer.
Table 10. SPI write address
Address line Bit 7 Bit 6
(MOSI)
(MSB)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)^[1]
byte 0
0
address address address address address address reserved
byte 1 to byte data data
data
data
data
data
data
data
n+1
[1] All reserved bits must be set to logic 0.
Remark: The data bus pins D7 to D0 must be disconnected.
Refer to Section 13.4.4 on page 95 for the timing specification.
MFRC530_33
Product data sheet
PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.3 — 6 July 2010
057433
© NXP B.V. 2010. All rights reserved.
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