SAA4952WP Datasheet, PDF (7/32 Pages) NXP Semiconductors – Memory controller

Philips Semiconductors
Memory controller
Objective specification
SAA4952WP
By changing the active MPIP in a sequence all PIPs are
sequentially updated.
The second Multi-PIP option needs an extra PIP module.
This module produces a PIP picture which is originally
displayed at the bottom right position of the screen.
The information of the PIP picture is stored at a desired
position in the field memories. Depending on the
compression mode of the PIP module, the MPIP display
can be configured via software control
(e.g. 4 × 3, 4 × 4, etc.).
For basic features and PALplus systems a 50 Hz/1f_H
single clock mode is provided. Switching between a 2f_H
and the 1f_H mode is performed by the SAA4952WP
hardware pin SHF to avoid wrong HDFL frequencies
which might occur in the event of a software controlled
selection. For the same reason the deflection processor is
selected via pin SDP, whereas in the case of the TDA9152
or another deflection processor without the need of a
constant 27 MHz clock, only two PLLs are necessary.
ICs from the new IC generation such as PALplus,
LIMERIC and PAN-IC need to be supplied with two clocks.
The frequency of one clock equals the frequency of the
output data (13.5, 16 or 18 MHz). A second clock operates
with twice the frequency (27, 32 or 36 MHz).
The SAA4952WP generates the necessary signals,
whereas SWC05 is obtained by dividing LLA by a factor of
two.
The display section can be set into a fixed mode via the
microcontroller port. This allows a generator mode
function for displaying OSD without a stable input signal.
A still picture can be shown on the screen completely
decoupled from the input of the converter. The generator
mode can also be used if the MPIP function is activated.
Microcontroller interface
The SAA4952WP is connected to a microcontroller via
pins P0 to P7, ALE and WRD. This controller receives
commands from the I²C-bus and sets the register of the
SAA4952WP accordingly. Figure 3 shows the timing of
these signals. Address and data are transmitted
sequentially on the bus with the falling edge of ALE
denoting a valid address and the falling edge of WRD
denoting valid data. The individual registers, their address
and their function are listed in Tables 1 to 12. Various
START and STOP registers are 9 bits wide, in this
instance the MSB is combined with MSBs of other signals
or fine delay control bits in an extra control register which
has to be addressed and loaded separately.
In order to load the proper values to the vertical control
registers (VWE2, VRE1 and VRE2) in the event of e.g.
median filtering, information about the current 100 Hz field
is necessary. To obtain this data, the microcontroller
sends the address 80H (read mode) which puts the
SAA4952WP in output mode for the next address/data
cycle. For this one cycle the WRD pin works as a RDN pin.
The microcontroller is able to read the length of the
incoming fields. The length is measured in multiples of
32 µs. The result of the measurement is a 10-bit data
word. The first 8 bits can be accessed under read address
81H. Register 80H contains the MSB and the 9th bit.
The exact knowledge of the field length makes it possible
to decide in which standard the input signal was
transmitted. The microcontroller is able to detect
non-standard sources such as a VCR in trick modes. It is
also possible to decide whether the input is interlaced or
non-interlaced. The vertical control signals to the
memories are adapted to the source to obtain a stable
display.
handbook, fu_All_Lp_Eagewidth
WRD
DATA
ADDRESS
1997 Jun 10
DATA
ADDRESS
DATA
Fig.3 Microcontroller interface timing.
7
ADDRESS
MGH133