 English |
|
|
|
|
|
|
|
| SAA4952WP Datasheet, PDF (20/32 Pages) NXP Semiconductors – Memory controller | |||
| |||
| ◁ |
Philips Semiconductors
Memory controller
Objective speciï¬cation
SAA4952WP
handbook, full pagewidVtAh CQ
VWE1
Vr(WE1)(1)
RSTW1
Vf(WE1)(2)
(1) Vr(WE1) = Nr à line.
(2) Vf(WE1) = Nf à line.
Fig.5 Vertical acquisition timing.
MHA726
handbook, full pagewidth
HRD or
HRDFL
HDSP(1)
HVSP(2)
HDSPr
HVSPn(2)
HDSPf
(1) HDSP = BLND, HRE and HWE2.
(2) HVSP consists of the 4 pulses HVSP1 to HVSP4 (HVSPn).
Fig.6 Programmable horizontal display signals.
1997 Jun 10
20
MHA727
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese