PSMN4R0-25YLC Datasheet, PDF (7/15 Pages) NXP Semiconductors – N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK

NXP Semiconductors
PSMN4R0-25YLC
N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK
Table 6. Characteristics …continued
Symbol
Parameter
Conditions
t_d(on)
t_r
t_d(off)
t_f
Q_oss
turn-on delay time
rise time
turn-off delay time
fall time
output charge
Source-drain diode
V_DS = 12 V; R_L = 0.5 Ω; V_GS = 4.5 V;
R_G(ext) = 4.7 Ω
V_GS = 0 V; V_DS = 12 V; f = 1 MHz;
T_j = 25 °C
V_SD
source-drain voltage I_S = 20 A; V_GS = 0 V; T_j = 25 °C;
see Figure 17
t_rr
reverse recovery time I_S = 20 A; dI_S/dt = -100 A/µs; V_GS = 0 V;
Q_r
recovered charge
V_DS = 12 V
t_a
reverse recovery rise V_GS = 0 V; I_S = 20 A; dI_S/dt = -100 A/µs;
time
V_DS = 12 V; see Figure 18
t_b
reverse recovery fall
time
Min Typ Max Unit
-
15.9 -
ns
-
17.5 -
ns
-
24
-
ns
-
9.9 -
ns
-
7.32 -
nC
-
0.8 1.1 V
-
24.5 -
ns
-
16.1 -
nC
-
14.9 -
ns
-
9.6 -
ns
80
10 3.5
ID
(A)
4.5
60
40
003aaf 508
3.0
VGS (V) = 2.8
2.6
16
RDS on
(m)
12
8
003aaf 509
20
2.4
2.2
0
0
1
2
3
4
VDS (V)
4
0
0
4
8
12
16
VGS (V)
Fig 6. Output characteristics; drain current as a
Fig 7. Drain-source on-state resistance as a function
function of drain-source voltage; typical values
of gate-source voltage; typical values
PSMN4R0-25YLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 2 December 2010
© NXP B.V. 2010. All rights reserved.
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