PSMN4R0-25YLC Datasheet, PDF (3/15 Pages) NXP Semiconductors – N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK

NXP Semiconductors
PSMN4R0-25YLC
N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V_DS
V_DGR
V_GS
I_D
I_DM
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
Conditions
T_j ≥ 25 °C; T_j ≤ 175 °C
25 °C ≤ T_j ≤ 175 °C; R_GS = 20 kΩ
V_GS = 10 V; T_mb = 25 °C; see Figure 1
V_GS = 10 V; T_mb = 100 °C; see Figure 1
pulsed; t_p ≤ 10 µs; T_mb = 25 °C;
see Figure 4
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
T_sld(M)
peak soldering temperature
V_ESD
electrostatic discharge voltage
Source-drain diode
T_mb = 25 °C; see Figure 2
MM (JEDEC JESD22-A115)
I_S
source current
I_SM
peak source current
Avalanche ruggedness
T_mb = 25 °C
pulsed; t_p ≤ 10 µs; T_mb = 25 °C
E_DS(AL)S
non-repetitive drain-source
avalanche energy
V_GS = 10 V; T_j(init) = 25 °C; I_D = 84 A;
V_sup ≤ 25 V; R_GS = 50 Ω; unclamped;
see Figure 3
Min Max Unit
-
25 V
-
25 V
-20 20 V
-
84 A
-
60 A
-
336 A
-
61 W
-55 175 °C
-55 175 °C
-
260 °C
200 -
V
-
55 A
-
336 A
-
17.4 mJ
100
ID
(A)
80
60
40
20
0
0
003aaf 505
50
100
150
200
Tmb ( C)
120
P_der
(%)
80
03na19
40
0
0
50
100
150
200
T_mb (°C)
Fig 1. Continuous drain current as function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN4R0-25YLC
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 2 December 2010
© NXP B.V. 2010. All rights reserved.
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