PSMN005-25D Datasheet, PDF (7/9 Pages) NXP Semiconductors – N-channel logic level TrenchMOS transistor

Philips Semiconductors
N-channel logic level TrenchMOS™ transistor
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads
(one lead cropped)
Product specification
PSMN005-25D
SOT428
seating plane
y
A
E
A
A2
b2
A1
D1
mounting
base
E1
D
HE
L2
2
1
L
3
b1
e
b
wM A
e1
L1
c
0
10 20 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1⁽¹⁾
A2
b
b1
max.
b2
c
D D1 E ^E1
max. max. max. min.
e
e1
HE
max.
L
L1
min.
L2
mm ^{2.38 0.65 0.89 0.89}
2.22 0.45 0.71 0.71
1.1
0.9
5.36
5.26
0.4
0.2
6.22 4.81 6.73
5.98 4.45 6.47
4.0
2.285 4.57
10.4
9.6
2.95
2.55
0.5
0.7
0.5
Note
1. Measured from heatsink back to lead.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
EIAJ
EUROPEAN
PROJECTION
w
y
max.
0.2 0.2
ISSUE DATE
SOT428
98-04-07
Fig.16. SOT428 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
October 1999
7
Rev 1.100