BUK107-50GL Datasheet, PDF (7/10 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK107-50GL
VDD
RL
D
TOPFET
VDS
measure
I
P
D.U.T.
VIS
S
0V
Fig.14. Test circuit for resistive load switching times.
V_IS = 5 V
15 ^{VIS & VDS / V}
BUK107-50GL
VDS
10
VIS
5
IDSS
10 uA
BUK107-50GL
1 uA
100 nA
10 nA
-50
0
50
100
150
Tj / C
Fig.16. Typical drain source leakage current
I_DSS = f(T_j); conditions: V_DS = 40 V; V_IS = 0 V.
0
-20 0
20 40 60 80 100 120 140 160 180
time / us
Fig.15. Typical switching waveforms, resistive load .
R_L = 50 Ω; adjust V_DD to obtain I_D = 250 mA; T_j = 25˚C
1E+02
Zth j-amb / (K/W)
D=
0.5
BUK107-50GL
1E+01
0.2
0.1
0.05
0.02
1E+00
P_D
tp
D=
tp
T
1E-01
1E-02
0
1E-07
1E-05
1E-03
1E-01
T
1E+01
t
1E+03
t/s
Fig.17. Transient thermal impedance, TOPFET mounted on PCB of fig 19.
Z_{th j-amb} = f(t); parameter D = t_p/T
April 1998
7
Rev 1.200