BUK100-50DL Datasheet, PDF (7/10 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK100-50DL
ID / A
20
BUK100-50DL
15
typ.
10
5
0
50
60
70
VDS / V
Fig.12. Typical clamping characteristics, 25 ˚C.
I_D = f(V_DS); conditions: V_IS = 0 V; t_p ≤ 50 µs
VIS(TO) / V
2
1
max.
typ.
min.
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.13. Input threshold voltage.
V_IS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = 5 V
IISL & IIS / uA
600
BUK100-50DL
500
PROTECTION LATCHED
400
IISL
300
RESET
IIS
200
100
NORMAL
0
0
2
4
6
VIS / V
Fig.14. Typical DC input characteristics, T_j = 25 ˚C.
I_ISL & I_IS = f(V_IS); protection latched & normal operation
IS / A
60
BUK100-50DL
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1
1.2 1.4
VSD / V
Fig.15. Typical reverse diode current, T_j = 25 ˚C.
I_S = f(V_SDS); conditions: V_IS = 0 V; t_p = 250 µs
VDD
RL
D
TOPFET
I
P
D.U.T.
RI
VIS
S
ID measure
0V
0R1
Fig.16. Test circuit for resistive load switching times.
VIS / V & VDS / V
VDS
10
VIS
5
BUK100-50DL
0
0
100
200
300
400
time / us
Fig.17. Typical switching waveforms, resistive load.
V_DD = 13 V; R_L = 4 Ω; R_I = 50 Ω, T_j = 25 ˚C.
November 1996
7
Rev 1.200