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74HC74 Datasheet, PDF (7/22 Pages) NXP Semiconductors – Dual D-type flip-flop with set and reset; positive-edge trigger
Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
Product specification
74HC74; 74HCT74
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER
CONDITIONS
VCC
VI
VO
Tamb
tr, tf
supply voltage
input voltage
output voltage
operating ambient
temperature
input rise and fall
times
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
74HC74
74HCT74
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
2.0 5.0 6.0 4.5 5.0 5.5 V
0
−
VCC
0
−
VCC
V
0
−
VCC
0
−
VCC
V
−40 +25 +125 −40 +25 +125 °C
−
−
1000 −
−
500 ns
−
6.0 500 −
6.0 500 ns
−
−
400 −
−
500 ns
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
VCC
supply voltage
IIK
input diode current
IOK
output diode current
IO
ICC, IGND
Tstg
Ptot
output source or sink current
VCC or GND current
storage temperature
power dissipation
CONDITIONS
MIN.
−0.5
VI < −0.5 V or VI > VCC + 0.5 V; −
note 1
VO < −0.5 V or VO > VCC + 0.5 V; −
note 1
−0.5 V < VO < VCC + 0.5 V; note 1 −
−
−65
Tamb = −40 to +125 °C; note 2
−
MAX.
+7.0
±20
UNIT
V
mA
±20
mA
±25
mA
±100
mA
+150
°C
500
mW
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
For DIP14 packages: above 70 °C derate linearly with 12 mW/K.
2003 Jul 10
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