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74HC74 Datasheet, PDF (12/22 Pages) NXP Semiconductors – Dual D-type flip-flop with set and reset; positive-edge trigger | |||
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Philips Semiconductors
Dual D-type ï¬ip-ï¬op with set and reset;
positive-edge trigger
Product speciï¬cation
74HC74; 74HCT74
Family 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS
VCC (V)
MIN.
Tamb = â40 to +85 °C
tPHL/tPLH
propagation
see Fig.7
delay nCP to nQ, nQ
propagation
see Fig.8
delay nSD to nQ, nQ
propagation
see Fig.8
delay nRD to nQ, nQ
tTHL/tTLH
tW
output transition time see Fig.7
clock pulse width HIGH see Fig.7
or LOW
set or reset pulse width see Fig.8
LOW
trem
removal time set or
see Fig.8
reset
tsu
set-up time nD to nCP see Fig.7
th
hold time nCP to nD see Fig.7
fmax
maximum clock pulse see Fig.7
frequency
4.5
â
4.5
â
4.5
â
4.5
â
4.5
23
4.5
20
4.5
8
4.5
15
4.5
+3
4.5
22
Tamb = â40 to +125 °C
tPHL/tPLH
propagation
see Fig.7
delay nCP to nQ, nQ
propagation
see Fig.8
delay nSD to nQ, nQ
propagation
see Fig.8
delay nRD to nQ, nQ
tTHL/tTLH
tW
output transition time see Fig.7
clock pulse width HIGH see Fig.7
or LOW
set or reset pulse width see Fig.8
LOW
trem
removal time set or
see Fig.8
reset
tsu
set-up time nD to nCP see Fig.7
th
hold time nCP to nD see Fig.7
fmax
maximum clock pulse see Fig.7
frequency
4.5
â
4.5
â
4.5
â
4.5
â
4.5
27
4.5
24
4.5
9
4.5
18
4.5
3
4.5
18
TYP.
18
23
24
7
9
9
1
5
â3
54
â
â
â
â
â
â
â
â
â
â
MAX.
44
50
50
19
â
â
â
â
â
â
53
60
60
22
â
â
â
â
â
â
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
2003 Jul 10
12
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