74F3893 Datasheet, PDF (7/10 Pages) NXP Semiconductors – Quad futurebus backplane transceiver

Philips Semiconductors
Quad Futurebus backplane transceiver
Product specification
74F3893
AC WAVEFORMS
DE, Dn
2V
I/On
1V
V_M
t_PHL
V_M
V_M
t_PLH
90%
t_THL
V_M
10%
90%
t_TLH
10%
SF00577
Waveform 1. Propagation delay for driver
RE
V_M
V_M
t_PZH
t_PHZ
V_OH -0.3V
Rn
V_M
0V
SF00579
Waveform 3. 3–state output enable time to high level
and output disable time from high level
2V
I/On
1V
Rn
V_M
V_M
t_PHL
V_M
t_PLH
V_M
SF00578
Waveform 2. Propagation delay for receiver
RE
V_M
V_M
t_PZL
t_PLZ
Rn
V_M
V_OL +0.3V
SF00580
Waveform 4. 3-state output enable time to low level
and output disable time from low level
Notes to AC waveforms
1. For all waveforms, V_M = 1.5V.
2. The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
TEST SWITCH
t_PLZ, t_PZL closed
V_CC
All other open
V_IN
V_OUT
R_L
PULSE
D.U.T.
GENERATOR
R_T
C_L R_L
Test circuit for 3–state outputs on D port
V_CC
7.0V
7.0V
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
t_w
V_M
10%
t_{THL (}t_f )
V_M
10%
t_{TLH (}t_r )
t_{TLH (}t_r )
90%
V_M
t_w
t_{THL (}t_f )
90%
V_M
90%
AMP (V)
Low V
AMP (V)
10%
Low V
V_IN
PULSE
GENERATOR
V_OUT
R_T
D.U.T.
R_T
C_D
Input pulse definition
INPUT PULSE REQUIREMENTS
family
amplitude Low V ^VM rep. rate
t_w
t_TLH
D port 3.0V 0.0V 1.5V 1MHz 500ns 2.5ns
I/O port 2.0V 1.0V 1.5V 1MHz
Test circuit for outputs on I/O port
DEFINITIONS:
R_L =
C_L =
R_U =
C_D =
R_T =
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Pull up resistor; see AC Electrical Characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Termination resistance should be equal to Z_OUT of pulse generators.
500ns 4.0ns
t_THL
2.5ns
4.0ns
SF00581
January 18, 1991
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