74F3893 Datasheet, PDF (3/10 Pages) NXP Semiconductors – Quad futurebus backplane transceiver

Philips Semiconductors
Quad Futurebus backplane transceiver
Product specification
74F3893
PIN CONFIGURATION
BG BUS
R0 D0 V_CCGND GND
3 2 1 20 19
D1 4
18 I/O0
R1 5
17 I/O1
LOGIC GND ⁶
PLCC
16 BUS GND
D2 7
15 I/O2
R2 8
14 I/O3
9 10 11 12 13
D3 R3 DE RE BUS
GND
SF00573
LOGIC SYMBOL
2479
11
DE
12
RE
D0 D1 D2 D3
I/O0 I/O1 1/O2 I/O3 R0 R1 R2 R3
V_CC = Pin 1,
LOGIC GND = Pin 8
18 17
BUS GND = Pin 13, 16, 19
BG GND = Pin 20
15 14
3 5 8 10
SF00574
IEC/IEEE SYMBOL
11
EN1
12
EN2
2
1D
2
4
7
9
3
18
5
17
7
15
9
14
SF00575
FUNCTION TABLE
INPUTS
INPUT/
OUT-
PUT
OUT-
PUT
DE RE Dn I/On
Rn
HL L
H
L
HLH
L
H
H H Dn
Dn
Z
LHX
H
Z
LLX
H
L
LLX
L
H
Notes to function table
1. H = High voltage level
2. L = Low voltage level
3. X = Don’t care
4. Z = High impedance ”off” state
OPERATING
MODE
Transmit to bus
Receiver 3–state,
transmit to bus
Receive, I/On = inputs
LOGIC DIAGRAM
2
D0
R0 ³
4
D1
5
R1
D2 ⁷
V_CC = Pin 1
LOGIC GND = Pin 6
BUS GND = Pin 13, 16, 19
BG GND = Pin 20
R2 ⁸
9
D3
R3 ¹⁰
11
DE
18
I/O0
17 _I/O1
12 _RE
15
I/O2
14 _I/O3
SF00576
January 18, 1991
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