LPC1850_1112 Datasheet, PDF (62/157 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD, and external memory controller

NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
Table 3. Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
Description
CLK2
D14 x
CLK3
P12 x
Debug pins
DBGEN
L4 x
TCK/SWDCLK J5 x
TRST
TMS/SWDIO
M4 x
K6 x
TDO/SWO
K5 x
TDI
J4 x
USB0 pins
USB0_DP
F2 x
USB0_DM
G2 x
USB0_VBUS F1 x
K6 141 99 68 ^[5] O; O EMC_CLK3 — SDRAM clock 3.
PU _{O CLKOUT — Clock output pin.}
- R — Function reserved.
- R — Function reserved.
I/O SD_CLK — SD/MMC card clock.
O EMC_CLK23 — SDRAM clock 2 and clock 3
combined.
O I2S0_TX_MCLK — I²S transmit master clock.
I/O I2S1_RX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to
the signal SCK in the I²S-bus specification.
- - - - ^[5] O; O EMC_CLK2 — SDRAM clock 2.
PU _{O CLKOUT — Clock output pin.}
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
O CGU_OUT1 — CGU spare clock output 1.
- R — Function reserved.
I/O I2S1_RX_SCK — Receive Clock. It is driven by the
master and received by the slave. Corresponds to
the signal SCK in the I²S-bus specification.
A6 41 28 18 ^[3] I
I JTAG interface control signal. Also used for boundary
scan.
H2 38 27 17 ^[3] I; F I
Test Clock for JTAG interface (default) or Serial Wire
(SW) clock.
B4 42 29 19 ^[3] I; PU I Test Reset for JTAG interface.
C4 44 30 20 ^[3] I; PU I
Test Mode Select for JTAG interface (default) or SW
debug data input/output.
H3 46 31 21 ^[3] O
O Test Data Out for JTAG interface (default) or SW
trace output.
G3 35 26 16 ^[3] I; PU I Test Data In for JTAG interface.
E1 26 18 9 ^[7] -
E2 28 20 11 ^[7] -
E3 29 21 12 ^[7] -
[8]
I/O USB0 bidirectional D+ line.
I/O USB0 bidirectional D line.
I/O VBUS pin (power on USB cable). This pin includes
an internal pull-down resistor of 64 k (typical) 
16 k.
LPC1850_30_20_10
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
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