TDA8359J Datasheet, PDF (6/20 Pages) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS

Philips Semiconductors
Full bridge vertical deflection output circuit
in LVDMOS
Product specification
TDA8359J
CHARACTERISTICS
V_P = 12 V; V_FB = 45 V; f_vert = 50 Hz; V_I(bias) = 880 mV; T_amb = 25 °C; measured in test circuit of Fig.3; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Supplies
V_P
V_FB
I_q(P)(av)
I_q(P)
I_q(FB)(av)
operating supply voltage
flyback supply voltage
average quiescent supply current
quiescent supply current
average quiescent flyback supply
current
note 1
during scan
no signal; no load
during scan
7.5
12
18
V
2 × V_P 45
66
V
−
10
15
mA
−
45
75
mA
−
−
10
mA
Inputs A and B
V_i(p-p)
input voltage (peak-to-peak value) note 2
−
V_I(bias)
input bias voltage
note 2
100
I_I(bias)
input bias current
source
−
Outputs A and B
V_loss(1)
voltage loss first scan part
note 3
I_o = 1.1 A
−
I_o = 1.6 A
−
V_loss(2)
voltage loss second scan part
note 4
I_o = −1.1 A
−
I_o = −1.6 A
−
I_o(p-p)
output current
−
(peak-to-peak value)
LE
linearity error
V_offset
offset voltage
∆V_offset(T) offset voltage variation with
temperature
I_o(p-p) = 3.2 A; notes 5 and 6
adjacent blocks
−
non adjacent blocks
−
across R_M; V_i(dif) = 0 V
V_I(bias) = 200 mV
−
V_I(bias) = 1 V
−
across R_M; V_i(dif) = 0 V
−
V_O
DC output voltage
V_i(dif) = 0 V
−
G_v(ol)
open-loop voltage gain
notes 7 and 8
−
f_{− 3dB(h)}
high −3 dB cut-off frequency
open-loop
−
G_v
voltage gain
note 9
−
∆G_v(T)
voltage gain variation with the
−
temperature
PSRR
power supply rejection ratio
note 10
80
1000 1500 mV
880
1600 mV
25
35
µA
−
4.5
V
−
6.6
V
−
3.3
V
−
4.8
V
−
3.2
A
1
2
%
1
3
%
−
±15
−
±20
−
40
0.5 × V_P −
60
−
1
−
1
−
−
10^−4
90
−
mV
mV
µV/K
V
dB
kHz
K^−1
dB
2002 Jan 21
6