TDA8359J Datasheet, PDF (3/20 Pages) NXP Semiconductors – Full bridge vertical deflection output circuit in LVDMOS

Philips Semiconductors
Full bridge vertical deflection output circuit
in LVDMOS
Product specification
TDA8359J
BLOCK DIAGRAM
handbook, full pagewidth
VI(bias)
0
Vi(p-p)
Vi(p-p)
VI(bias)
0
GUARD
VP
VFB
8
GUARD
CIRCUIT
INA 1
INPUT
AND
FEEDBACK
CIRCUIT
INB ₂
3
6
M5
D2
D3
M2
D1
M4
7 ^OUTA
9
FEEDB
M1
4 OUTB
M3
TDA8359J
5
GND
Fig.1 Block diagram.
MGL862
PINNING
SYMBOL
INA
INB
V_P
OUTB
GND
V_FB
OUTA
GUARD
FEEDB
PIN
DESCRIPTION
1 input A
2 input B
3 supply voltage
4 output B
5 ground
6 flyback supply voltage
7 output A
8 guard output
9 feedback input
handbook, halfpage
INA 1
INB 2
VP 3
OUTB 4
GND 5 _TDA8359J
VFB 6
OUTA 7
GUARD 8
FEEDB 9
MGL863
The exposed die pad is connected to pin GND.
Fig.2 Pin configuration.
2002 Jan 21
3