PSMN004-25B Datasheet, PDF (6/9 Pages) NXP Semiconductors – N-channel logic level TrenchMOS transistor

Philips Semiconductors
Product specification
N-channel logic level TrenchMOS™ transistor PSMN004-25B, PSMN004-25P
Gate-source voltage, VGS (V)
15
14 ^{ID = 75 A}
13 VDD = 15 V
12 _{Tj = 25 C}
11
10
9
8
7
6
5
4
3
2
1
0
0 25 50 75 100 125 150 175 200 225 250
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G)
Source-Drain Diode Current, IF (A)
100
VGS = 0 V
90
80
70
60
50
40
175 C
30
Tj = 25 C
20
10
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Source-Drain Voltage, VSDS (V)
1.1 1.2
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
Maximum Avalanche Current, IAS (A)
100
25 C
Tj prior to avalanche = 150 C
10
1
0.001
0.01
0.1
1
10
Avalanche time, tAV (ms)
Fig.15. Maximum permissible non-repetitive
avalanche current (I_AS) versus avalanche time (t_AV);
unclamped inductive load
October 1999
6
Rev 1.100