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| LPC4350_12 Datasheet, PDF (6/149 Pages) NXP Semiconductors – 32-bit ARM Cortex-M4/M0 MCU; up to 264 kB SRAM; Ethernet; two High-speed USBs; advanced configurable peripherals | |||
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NXP Semiconductors
5. Block diagram
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
LPC4350/30/20/10
TEST/DEBUG
INTERFACE
ARM
CORTEX-M4
HIGH-SPEED PHY
GPDMA
ETHERNET(1)
10/100
MAC
IEEE 1588
HIGH-SPEED
USB0(1)
HOST/
DEVICE/OTG
HIGH-SPEED
USB1(1)
HOST/DEVICE
LCD(1)
AHB MULTILAYER MATRIX
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
SD/
MMC
masters
slaves
BRIDGE 0
BRIDGE 1
BRIDGE 2
BRIDGE 3
WWDT
USART0
UART1
SSP0
TIMER0
TIMER1
SCU
GPIO
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
MOTOR
CONTROL
PWM(1)
I2C0
I2S0
I2S1
C_CAN1
RI TIMER
USART2
USART3
TIMER2
TIMER3
SSP1
QEI(1)
GIMA
I2C1
10-bit DAC
C_CAN0
10-bit ADC0
10-bit ADC1
BRIDGE
CGU
CCU1
CCU2
RGU
slaves
BRIDGE
ALARM TIMER
BACKUP REGISTERS
POWER MODE CONTROL
CONFIGURATION
REGISTERS
EVENT ROUTER
OTP MEMORY
RTC
RTC OSC
12 MHz IRC
RTC POWER DOMAIN
128 kB LOCAL SRAM
72 kB LOCAL SRAM
64 kB ROM
32 kB AHB SRAM
16 +16 kB AHB SRAM
SCT
EMC
HS GPIO
AES
SPI
SGPIO
SPIFI
= connected to GPDMA
(1) Not available on all parts (see Table 2).
Fig 1. LPC4350/30/20/10 Block diagram
002aaf772
LPC4350_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3.1 â 5 January 2012
© NXP B.V. 2012. All rights reserved.
6 of 149
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