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BUK755R4-100E_15 Datasheet, PDF (6/13 Pages) NXP Semiconductors – N-channel TrenchMOS standard level FET
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NXP Semiconductors
BUK755R4-100E
N-channel TrenchMOS standard level FET
Symbol
Parameter
Conditions
Ciss
input capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 15
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 80 V; RL = 3.2 Ω; VGS = 10 V;
RG(ext) = 5 Ω
td(off)
turn-off delay time
tf
fall time
LD
internal drain
from upper edge of drain mounting
inductance
base to centre of die
from drain lead 6mm from package to
centre of die
LS
internal source
from source lead to source bond pad
inductance
Source-drain diode
VSD
source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 16
trr
reverse recovery time IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 25 V
Min Typ Max Unit
-
8860 11810 pF
-
770 925 pF
-
546 750 pF
-
37
-
ns
-
62
-
ns
-
158 -
ns
-
80
-
ns
-
2.5 -
nH
-
4.5 -
nH
-
7.5 -
nH
-
0.77 1.2 V
-
65
-
ns
-
191 -
nC
360
ID
(A)
240
VGS(V) = 10
003aai249
7
6
5.5
10
RDSon
(mΩ)
7.5
003aai250
5
5
120
2.5
4.5
0
0
1
2 VDS(V) 3
0
0
5
10
15 VGS(V) 20
Fig. 6.
Tj = 25 °C; tp = 300 μs
Output characteristics; drain current as a
function of drain-source voltage; typical values
Fig. 7.
Drain-source on-state resistance as a function
of gate-source voltage; typical values
BUK755R4-100E
Product data sheet
All information provided in this document is subject to legal disclaimers.
11 September 2012
© NXP B.V. 2012. All rights reserved
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