83C752 Datasheet, PDF (6/24 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count
Product specification
83C752/87C752
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
IDLE MODE
The 8XC752 includes the 80C51 power-down and idle mode
features. In idle mode, the CPU puts itself to sleep while all of the
on-chip peripherals except the A/D and PWM stay active. The
functions that continue to run while in the idle mode are Timer 0, the
I²C interface including Timer I, and the interrupts. The instruction to
invoke the idle mode is the last instruction executed in the normal
operating mode before the idle mode is activated. The CPU
contents, the on-chip RAM, and all of the special function registers
remain intact during this mode. The idle mode can be terminated
either by any enabled interrupt (at which time the process is picked
up at the interrupt service routine and continued), or by a hardware
reset which starts the processor in the same manner as a power-on
reset. Upon powering-up the circuit, or exiting from idle mode,
sufficient time must be allowed for stabilization of the internal analog
reference voltages before an A/D conversion is started.
Special Function Registers
The special function registers (directly addressable only) contain all
of the 8XC751 registers except the program counter and the four
register banks. Most of the 21 special function registers are used to
control the on-chip peripheral hardware. Other registers include
arithmetic registers (ACC, B, PSW), stack pointer (SP) and data
pointer registers (DPH, DPL). Nine of the SFRs are bit addressable.
Data Pointer
The data pointer (DPTR) consists of a high byte (DPH) and a low
byte (DPL). In the 80C51 this register allows the access of external
data memory using the MOVX instruction. Since the 83C752 does
not support MOVX or external memory accesses, this register is
generally used as a 16-bit offset pointer of the accumulator in a
MOVC instruction. DPTR may also be manipulated as two
independent 8-bit registers.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction
to invoke power-down is the last instruction executed. Only the
contents of the on-chip RAM are preserved. A hardware reset is the
only way to terminate the power-down mode. The control bits for the
reduced power modes are in the special function register PCON.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE
Port 0*
Port 1
Port 2
Idle
Power-down
Data
Data
* Except for PWM output (P0.4).
Data
Data
Data
Data
DIFFERENCES BETWEEN THE 8XC752 AND
THE 80C51
Program Memory
On the 8XC752, program memory is 2048 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. If these instructions are executed, the
appropriate number of instruction cycles will take place along with
external fetches; however, no operation will take place. The LJMP
may not respond to all program address bits. The only fixed
locations in program memory are the addresses at which execution
is taken up in response to reset and interrupts, which are as follows:
Program Memory
Event
Address
Reset
000
External INT0
003
Counter/timer 0
00B
External INT1
013
Timer I
01B
I²C serial
023
ADC
02B
PWM
033
Memory Organization
The 8XC752 manipulates operands in three memory address
spaces. The first is the program memory space which contains
program instructions as well as constants such as look-up tables.
The program memory space contains 2k bytes in the 8XC752.
The second memory space is the data memory array which has a
logical address space of 128 bytes. However, only the first 64 (0 to
3FH) are implemented in the 8XC752.
The third memory space is the special function register array having
a 128-byte address space (80H to FFH). Only selected locations in
this memory space are used (see Table 2). Note that the
architecture of these memory spaces (internal program memory,
internal data memory, and special function registers) is identical to
the 80C51, and the 8XC752 varies only in the amount of memory
physically implemented.
The 8XC752 does not directly address any external data or program
memory spaces. For this reason, the MOVX instructions in the
80C51 instruction set are not implemented in the 83C752, nor are
the alternate I/O pin functions RD and WR.
1998 May 01
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