83C752 Datasheet, PDF (12/24 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count

Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I²C, PWM, low pin count
Product specification
83C752/87C752
COUNTER/TIMER
The 8XC752 counter/timer is designated Timer 0 and is separate
from Timer I of the I²C serial port and from the PWM. Its operation is
similar to mode 2 of the 80C51 counter/timer, extended to 16 bits.
When Timer 0 is used in the external counter mode, the T0 input
(P1.7) is sampled every S4P1. The counter/timer function is
controlled using the timer control register (TCON).
TCON Register
MSB
LSB
GATE
C/T
TF
TR
IE0
IT0
IE1
IT1
Position Symbol
Function
TCON.7 GATE 1 – Timer 0 is enabled only when INT0 pin is
high and TR is 1.
0 – Timer 0 is enabled only when TR is 1.
TCON.6 C/T 1 – Counter operation from T0 pin.
0 – Timer operation from internal clock.
TCON.5 TF 1 – Set on overflow of T0.
0 – Cleared when processor vectors to interrupt
routine and by reset.
TCON.4 TR 1 – Enable timer 0
0 – Disable timer 0
TCON.3 IE0 1 – Edge detected on INT0
TCON.2 IT0 1 – INT0 is edge triggered.
0 – INT0 is level sensitive.
TCON.1 IE1 1 – Edge detected on INT1
TCON.0 IT1 1 – INT1 is edge triggered.
0 – INT1 is level sensitive.
These flags are functionally identical to the corresponding 80C51
flags except that there is only one of the 80C51 style timers, and the
flags are combined into one register.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
A communications watchdog timer, Timer I, is described in the I²C
section. In I²C applications, this timer is dedicated to time generation
and bus monitoring for the I²C. In non-I²C applications, it is available
for use as a fixed time base.
The 16-bit timer/counter’s operation is similar to mode 2 operation
on the 80C51, but is extended to 16 bits. The timer/counter is
clocked by either 1/12 the oscillator frequency or by transitions on
the T0 pin. The C/T pin in special function register TCON selects
between these two modes. When the TCON TR bit is set, the
timer/counter is enabled. Register pair TH and TL are incremented
by the clock source. When the register pair overflows, the register
pair is reloaded with the values in registers RTH and RTL. The value
in the reload registers is left unchanged. The TF bit in special
function register TCON is set on counter overflow and, if the
interrupt is enabled, will generate an interrupt (see Figure 3).
OSC
÷ 12
T0 Pin
TR
C/T = 0
C/T = 1
TL
TH
TF
Int.
Reload
Gate
INT0 Pin
RTL
RTH
Figure 3. 83C752 Counter/Timer Block Diagram
Table 3. I²C Special Function Register Addresses
REGISTER ADDRESS
BIT ADDRESS
NAME
I²C control
I²C data
I²C configuration
I²C status
SYMBOL
I2CON
I2DAT
I2CFG
I2STA
ADDRESS MSB
98
9F
9E
9D
9C
9B
99
–
–
–
–
–
D8
DF
DE
DD
DC
DB
F8
FF
FE
FD
FC
FB
SU00300
LSB
9A
99
98
–
–
–
DA
D9
D8
FA
F9
F8
1998 May 01
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