74HC_HCT595_15 Datasheet, PDF (6/24 Pages) NXP Semiconductors – 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6+&3
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67&3
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4
4
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=VWDWH
4
4
46
Fig 8. Timing diagram
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=VWDWH
PQD
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
V_CC
supply voltage
I_IK
input clamping current
I_OK
output clamping current
I_O
output current
V_I < 0.5 V or V_I > V_CC + 0.5 V
V_O < 0.5 V or V_O > V_CC + 0.5 V
V_O = 0.5 V to (V_CC + 0.5 V)
pin Q7S
0.5 +7
V
-
20 mA
-
20 mA
-
25 mA
pins Qn
-
35 mA
I_CC
I_GND
T_stg
P_tot
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16 package
-
70
65
[1] _-
[2] _-
70
mA
-
mA
+150 C
750 mW
500 mW
SSOP16 package
[3] _-
500 mW
TSSOP16 package
[3] _-
500 mW
DHVQFN16 package
[4] _-
500 mW
[1] For DIP16 package: P_tot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: P_tot derates linearly with 8 mW/K above 70 C.
[3] For SSOP16 and TSSOP16 packages: P_tot derates linearly with 5.5 mW/K above 60 C.
[4] For DHVQFN16 package: P_tot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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