74HC_HCT595_15 Datasheet, PDF (5/24 Pages) NXP Semiconductors – 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state

NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6.2 Pin description
Table 2.
Symbol
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
Q7S
MR
SHCP
STCP
OE
DS
Q0
V_CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
parallel data output 1
parallel data output 2
parallel data output 3
parallel data output 4
parallel data output 5
parallel data output 6
parallel data output 7
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
parallel data output 0
supply voltage
7. Functional description
Table 3. Function table^[1]
Control
SHCP STCP OE MR
X
X
L
L
X

L
L
X
X
H
L

X
L
H
X

L
H


L
H
Input Output
DS Q7S Qn
X
L
NC
X
L
L
X
L
Z
H
Q6S NC
X
NC QnS
X
Q6S QnS
Function
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1] H = HIGH voltage state;
L = LOW voltage state;
 = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 26 January 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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