74HC40104 Datasheet, PDF (6/8 Pages) NXP Semiconductors – 4-bit bidirectional universal shift register; 3-state

Philips Semiconductors
4-bit bidirectional universal shift register;
3-state
Product specification
74HC/HCT40104
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: bus driver
I_CC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I_CC) for a unit load of 1 is given in the family specifications.
To determine ∆I_CC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
D₀ to D₃
D_SR, D_SL
CP
S₀, S₁
OE
UNIT LOAD COEFFICIENT
0.35
0.35
0.35
0.70
1.40
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF
T_amb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HCT
+25
−40 to +85
−40 to +125
UNIT
V_CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t_PHL/ t_PLH propagation delay
CP to Q_n
18 34
43
51 ns 4.5 Fig.6
t_PZH/ t_PZL 3-state output enable time
12 30
38
45 ns 4.5 Fig.8
OE to Q_n
t_PHZ/ t_PLZ 3-state output disable
time OE to Q_n
21 35
44
53 ns 4.5 Fig.8
t_THL/ t_TLH output transition time
5 12
15
18 ns 4.5 Fig.6
t_W
clock pulse width
16 7
20
24
ns 4.5 Fig.6
HIGH or LOW
t_su
set-up time
16 8
20
24
ns 4.5 Fig.8
D_n, D_SR, D_SL to CP
t_su
set-up time
S₀, S₁ to CP
20 9
25
30
ns 4.5 Fig.8
t_h
hold time
2 −2
2
2
ns 4.5 Fig.8
D_n, D_SR, D_SL to CP
t_h
hold time
S₀, S₁ to CP
2 −5
2
2
ns 4.5 Fig.8
f_max
maximum clock pulse
27 52
22
18
MHz 4.5 Fig.6
frequency
December 1990
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