74HC40104 Datasheet, PDF (2/8 Pages) NXP Semiconductors – 4-bit bidirectional universal shift register; 3-state

Philips Semiconductors
4-bit bidirectional universal shift
register; 3-state
Product specification
74HC/HCT40104
FEATURES
• Synchronous parallel or serial operating
• 3-state outputs
• Output capability: bus driver
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40104 are high-speed Si-gate CMOS
devices and are pin compatible with the “40104” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40104 are universal shift registers
featuring parallel inputs, parallel outputs, shift-right and
shift-left serial inputs and 3-state outputs allowing the
devices to be used in bus-organized systems.
In the parallel-load mode (S₀ and S₁ are HIGH), data is
loaded into the associated flip-flop and appears at the
output after the positive transition of the clock input (CP).
During loading, serial data flow is inhibited. Shift-right and
shift-left are accomplished synchronously on the positive
clock edge with serial data entered at the shift-right (D_SR)
and shift-left (D_SL) serial inputs, respectively.
Clearing the register is accomplished by setting both mode
controls (S₀ and S₁) LOW and clocking the register. When
the output enable input (OE) is LOW, all outputs assume
the high-impedance OFF-state (Z).
APPLICATIONS
• Arithmetic unit bus registers
• Serial/parallel conversion
• General-purpose register for bus organized systems
• General-purpose registers
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
t_PHL/ t_PLH
f_max
C_I
C_PD
PARAMETER
CONDITIONS
propagation delay CP to Q_n
maximum clock frequency
input capacitance
power dissipation capacitance per package
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
TYPICAL
HC
13
62
3.5
75
HCT
15
57
3.5
75
UNIT
ns
MHz
pF
pF
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2