74ABT161543 Datasheet, PDF (6/12 Pages) NXP Semiconductors – 16-bit latched transceiver with dual enable and master reset 3-State

Philips Semiconductors
16-bit latched transceiver with dual enable
and master reset (3-State)
Product specification
74ABT161543
74ABTH161543
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
V_CC
V_I
V_IH
V_IL
I_OH
I_OL
∆t/∆v
T_amb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature range
LIMITS
Min
Max
4.5
5.5
0
V_CC
2.0
0.8
–32
64
0
10
–40
+85
UNIT
V
V
V
V
mA
mA
ns/V
°C
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
T_amb = +25°C
MIN TYP MAX
T_amb = –40°C
to +85°C
MIN MAX
UNIT
V_IK
Input clamp voltage
V_CC = 4.5V; I_IK = –18mA
–1.2
–1.2 V
V_CC = 4.5V; I_OH = –3mA; V_I = V_IL or V_IH
2.5 3.0
2.5
V
V_OH
High-level output voltage
V_CC = 5.0V; I_OH = –3mA; V_I = V_IL or V_IH
3.0 3.6
3.0
V
V_CC = 4.5V; I_OH = –32mA; V_I = V_IL or V_IH
2.0 2.7
2.0
V
V_OL
V_RST
Low-level output voltage
Power-up output voltage³
V_CC = 4.5V; I_OL = 64mA; V_I = V_IL or V_IH
V_CC = 5.5V; I_O = 1mA; V_I = GND or V_CC
0.36 0.55
0.13 0.55
0.55 V
0.55 V
I_I
Input leakage
current
V_CC = 5.5V; V_I = GND or 5.5V
Control
pins
"0.01 ±1.0
±1.0 µA
I_HOLD
Bus Hold current A or B
Ports⁵ 74ABTH161543
V_CC = 4.5V; V_I = 0.8V
V_CC = 4.5V; V_I = 2.0V
V_CC = 5.5V; V_I = 0 to 5.5V
35
–75
±800
35
–75
µA
I_OFF
Power-off leakage current V_CC = 0.0V; V_O or V_I ≤ 4.5V
"1.0 ±100
±100 µA
I_PU/PD
Power-up/down 3-State
output current⁴
V_CC = 2.1V; V_O = 0.0V or V_CC;
V_I = GND or V_CC; V_OE = Don’t care
"1.0 ±50
±50 µA
I_IH + I_OZH 3-State output High current V_CC = 5.5V; V_O = 5.5V; V_I = V_IL or V_IH
1.0
50
50
µA
I_IL + I_OZL 3-State output Low current V_CC = 5.5V; V_O = 0.0V; V_I = V_IL or V_IH
–1.0 –50
–50 µA
I_CEX
Output High leakage current V_CC = 5.5V; V_O = 5.5V; V_I = GND or V_CC
1.0
50
50
µA
I_O
Output current¹
V_CC = 5.5V; V_O = 2.5V
–50 –100 –200 –50 –200 mA
I_CCH
V_CC = 5.5V; Outputs High, V_I = GND or V_CC
0.50 1.5
1.5 mA
I_CCL
I_CCZ
Quiescent supply current
V_CC = 5.5V; Outputs Low, V_I = GND or V_CC
V_CC = 5.5V; Outputs 3–State;
V_I = GND or V_CC
9
19
0.50 1.5
19 mA
1.5 mA
∆I_CC
Additional supply current
per input pin²
74ABT161543
V_CC = 5.5V; one input at 3.4V,
other inputs at V_CC or GND
5.0 100
100 µA
∆I_CC
Additional supply current
per input pin²
74ABTH161543
V_CC = 5.5V; one input at 3.4V,
other inputs at V_CC or GND
0.20
1
1
mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V_CC between 0V and 2.1V, with a transition time of up to 10msec. From V_CC = 2.1V to V_CC = 5V ± 10% a
transition time of up to 100µsec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
1998 Feb 27
6