ISP1161A1 Datasheet, PDF (53/136 Pages) NXP Semiconductors – Universal Serial Bus single-chip host and device controller

Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Table 21: HcFmInterval register: bit description
Bit
Symbol Description
31
FIT
FrameIntervalToggle: The HCD toggles this bit whenever it loads
a new value to FrameInterval.
30 to 16
FSMPS
[14:0]
FSLargestDataPacket (FSMaxPacketSize): Specifies a value
which is loaded into the Largest Data Packet Counter at the
beginning of each frame. The counter value represents the largest
amount of data in bits which can be sent or received by the HC in a
single transaction at any given time without causing a scheduling
overrun. The field value is calculated by the HCD.
15 to 14 -
reserved
13 to 0
FI[13:0]
FrameInterval: Specifies the interval between two consecutive
SOFs in bit times. The default value is 11999. The HCD must save
the current value of this field before resetting the HC. Setting the
HostControllerReset field of the HcCommandStatus register will
cause the HC to reset this field to its default value. HCD may
choose to restore the saved value upon completing the reset
sequence.
10.2.2 HcFmRemaining register (R: 0EH)
The HcFmRemaining register is a 14-bit down counter showing the bit time remaining
in the current frame.
Code (Hex): 0E — read
Table 22: HcFmRemaining register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
FRT
reserved
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00H
Access
R
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
FR[13:8]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
FR[7:0]
Reset
00H
Access
R
9397 750 13961
Product data
Rev. 03 — 23 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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