ISP1161A1 Datasheet, PDF (103/136 Pages) NXP Semiconductors – Universal Serial Bus single-chip host and device controller

Philips Semiconductors
ISP1161A1
USB single-chip host and device controller
Table 95:
Bit
3
2
1
0
DcEndpointStatusImage register: bit description…continued
Symbol
Description
OVERWRITE
This bit is set by hardware, a logic 1 indicating that a new Setup
packet has overwritten the previous set-up information, before it
was acknowledged or before the endpoint was stalled. If writing
the set-up data has finished, this bit is cleared by a read action.
Firmware must check this bit before sending an Acknowledge
Setup command or stalling the endpoint. Upon reading a logic 1
the firmware must stop ongoing set-up actions and wait for a
new Setup packet.
SETUPT
A logic 1 indicates that the buffer contains a Setup packet.
CPUBUF
This bit indicates which buffer is currently selected for CPU
access (0 = primary buffer, 1 = secondary buffer).
-
reserved
13.2.7 Acknowledge Setup (F4H)
This command acknowledges to the host that a Setup packet was received. The
arrival of a Setup packet disables the Validate Buffer and Clear Buffer commands for
the control IN and OUT endpoints. The microprocessor needs to re-enable these
commands by sending an Acknowledge Setup command, see Section 11.3.6.
Code (Hex): F4 — acknowledge set-up
Transaction — none
13.3 General commands
13.3.1 Read Endpoint Error Code (R: A0H–AFH)
This command returns the status of the last transaction of the selected endpoint, as
stored in the DcErrorCode register. Each new transaction overwrites the previous
status information. The bit allocation of the DcErrorCode register is shown in
Table 96.
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 word
Table 96: DcErrorCode register: bit allocation
Bit
7
6
5
4
Symbol
UNREAD DATA01 reserved
Reset
0
0
0
0
Access
R
R
R
R
3
2
ERROR[3:0]
0
0
R
R
1
0
RTOK
0
0
R
R
Table 97:
Bit
7
6
DcErrorCode register: bit description
Symbol
Description
UNREAD
A logic 1 indicates that a new event occurred before the
previous status was read.
DATA01
This bit indicates the PID type of the last successfully received
or transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).
9397 750 13961
Product data
Rev. 03 — 23 December 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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