TDA8426 Datasheet, PDF (5/24 Pages) NXP Semiconductors – Hi-fi stereo audio processor; I2C-bus

Philips Semiconductors
Hi-fi stereo audio processor; I²C-bus
Product specification
TDA8426
Bass control
The bass control stage can be switched from an emphasis of 15 dB to an attenuation of 12 dB for low frequencies in
steps of 3 dB.
Treble control
The treble control stage can be switched from +12 dB to −12 dB in steps of 3 dB.
Bias and power supply
The TDA8426 includes a bias and power supply stage, which generates a voltage of 0.5 × V_CC with a low output
impedance and injector currents for the logic part.
Power-on reset
The on-chip power-on reset circuit sets the mute bit to active, which mutes both parts of the treble amplifier. The muting
can be switched by transmission of the mute bit.
I²C-bus receiver and data handling
Bus specification
The TDA8426 is controlled via the 2-wire I²C-bus by a microcomputer.
The two wires (SDA − serial data, SCL − serial clock) carry information between the devices connected to the bus. Both
SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull up resistor.
When the bus is free both lines are HIGH.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW. The set up and hold times are specified in
AC CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as a start condition.
A LOW-to-HIGH transition of the SDA line while SCL is HIGH is defined as a stop condition.
The bus receiver will be reset by the reception of a start condition. The bus is considered to be busy after the start
condition.
The bus is considered to be free again after a stop condition.
Module address
Data transmission to the TDA8426 starts with the module address MAD.
March 1991
Fig.3 TDA8426 module address.
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