TDA8050A Datasheet, PDF (5/28 Pages) NXP Semiconductors – QPSK transmitter

Philips Semiconductors
QPSK transmitter
OUTEN 1
32 SW_CAP
BUF_OUT 2
31 RF_INC
BUF_OUTC 3
30 RF_IN
AGND2 4
29 AVCC2
I_IN 5
28 RF_OUT
I_INC 6
27 RF_OUTC
Q_IN 7
26 AVCC1
Q_INC 8
AGND1 9
25 IF_FILTC
TDA8050A
24 IF_FILT
TKAMOD 10
23 LOCK
TKBMOD 11
22 TKACONV
CP_MOD 12
21 TKBCONV
DVCC 13
20 TUNECONV
CLK 14
19 CP_CONV
DATA 15
18 DGND
EN 16
17 OSC_IN
FCE434
Fig.2 Pin configuration.
1999 Nov 05
Product specification
TDA8050A
FUNCTIONAL DESCRIPTION
The I and Q signals are balanced analog signals of
400 mV (p-p). These are mixed by two double balanced
mixers with the output signal generated by a first local
oscillator, to provide the modulated signal.
The modulated signal is then filtered by an IF filter. This
filtered signal, together a signal generated by a second
local oscillator, is converted by a balanced mixer to
produce the QPSK signal.
The QPSK signal is amplified by a gain controlled output
amplifier to a level suitable for transmission. The gain of
the amplifier is bus controlled and this amplifier can be
disabled when not transmitting, to provide signal
attenuation.
The amplified signal is applied to an on-chip amplifier with
two balanced outputs (open collector) connected to two
off-chip resistors (values 150 Ω), in turn connected to 9 V.
The balanced outputs drive a 2 : 1 transformer (Siemens
V944) loaded with 75 Ω, which gives an output level of
55 dBmV. The output frequency range of the transmitter is
5 to 65 MHz.
The frequency of the first local oscillator operates at twice
the frequency (i.e. 280 MHz), fixed by a PLL implemented
in the circuit.
The frequency of the second local oscillator operates in the
145 to 205 MHz bandwidth and can be programmed
through the PLL implemented in the circuit.
The VCOs of both the first and second local oscillators
need an external LC tank circuit with two varicap diodes.
The data sent to the PLL is loaded in bursts framed by
signal EN. Programming rising clock edges and their
appropriate data bits are ignored until EN goes active
(LOW). The internal latches are updated with the latest
programming data when EN returns to inactive (HIGH).
Only the last 14 bits are stored in the programming
register.
No check is made on the number of clock pulses received
during the time that programming is enabled. If EN goes
high while CLK is still LOW, a wrong active clock edge will
be generated, causing a shift of the data bits. At power up,
EN should be HIGH. The lock detector output LOCK is
HIGH when both PLLs are in lock.
The main divider ratio and the reference divider ratios are
provided via the serial bus. A control register controls the
Digital-to-Analog-Converter (DAC), the output amplifier
and the charge pump currents (see Tables 1, 2 and 3).
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