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| SSTUB32866 Datasheet, PDF (5/29 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications | |||
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NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 conï¬gurable registered buffer with parity
6. Pinning information
6.1 Pinning
SSTUB32866EC/G
ball A1 SSTUB32866EC/S
index area
123456
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aac011
Transparent top view
Fig 3. Pin conï¬guration for LFBGA96
SSTUB32866_2
Product data sheet
1
2
3
A DCKE PPO VREF
B
D2
D15
GND
C
D3
D16
D DODT QERR
VDD
GND
E
D5
F
D6
D17
VDD
D18
GND
G PAR_IN RESET
H CK
DCS
VDD
GND
J
CK
K
D8
CSR
D19
VDD
GND
L
D9
D20
VDD
M D10
D21
GND
N D11
D22
VDD
P D12
D23
GND
R D13
T D14
D24
VDD
D25 VREF
4
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
5
6
QCKE DNU
Q2
Q15
Q3
Q16
QODT DNU
Q5
Q17
Q6
Q18
C1
C0
QCS DNU
n.c.
n.c.
Q8
Q19
Q9
Q20
Q10
Q21
Q11
Q22
Q12
Q23
Q13
Q24
Q14
Q25
002aab108
Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0)
Rev. 02 â 9 October 2006
© NXP B.V. 2006. All rights reserved.
5 of 29
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