SSTUB32866 Datasheet, PDF (11/29 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 configurable registered buffer with parity
9. Recommended operating conditions
Table 7. Recommended operating conditions
Symbol Parameter
Conditions
V_DD
V_ref
V_T
V_I
V_IH(AC)
supply voltage
reference voltage
termination voltage
input voltage
AC HIGH-level input voltage
data (Dn), CSR, and
PAR_IN inputs
V_IL(AC) AC LOW-level input voltage
data (Dn), CSR, and
PAR_IN inputs
V_IH(DC) DC HIGH-level input voltage
data (Dn), CSR, and
PAR_IN inputs
V_IL(DC) DC LOW-level input voltage
data (Dn), CSR, and
PAR_IN inputs
V_IH
V_IL
V_ICR
HIGH-level input voltage
LOW-level input voltage
common mode input voltage
range
RESET, Cn
RESET, Cn
CK, CK
V_ID
I_OH
I_OL
T_amb
differential input voltage
HIGH-level output current
LOW-level output current
ambient temperature
CK, CK
operating in free air
SSTUB32866EC/G
SSTUB32866EC/S
Min
1.7
0.49 × V_DD
V_ref − 0.040
0
V_ref + 0.250
Typ
Max
-
2.0
0.50 × V_DD
V_ref
-
-
0.51 × V_DD
V_ref + 0.040
V_DD
-
Unit
V
V
V
V
V
-
-
V_ref − 0.250 V
V_ref + 0.125 -
-
V
-
-
[1] _{0.65 × VDD -}
[1] _-
-
[2] _0.675
-
V_ref − 0.125 V
-
V
0.35 × V_DD V
1.125
V
[2] ₆₀₀
-
-
mV
-
-
−8
mA
-
-
8
mA
0
-
70
°C
0
-
85
°C
[1] The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation.
[2] The differential inputs must not be floating, unless RESET is LOW.
SSTUB32866_2
Product data sheet
Rev. 02 — 9 October 2006
© NXP B.V. 2006. All rights reserved.
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