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| SSTUB32866 Datasheet, PDF (15/29 Pages) NXP Semiconductors – 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications | |||
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NXP Semiconductors
SSTUB32866
1.8 V DDR2-800 conï¬gurable registered buffer with parity
RESET
DCS
CSR
CK
m
m+1
m+2
m+3
m+4
CK
tsu
th
D1
to
D14
tPD
CK to Q
Q1
to
Q14
tsu
th
PAR_IN
tPD
CK to PPO
PPO
tPD
CK to QERR
tPD
CK to QERR
QERR
(not used)
002aaa656
Fig 8. Timing diagram for the ï¬rst SSTUB32866 (1 : 2 Register A conï¬guration) device used in pair; C0 = 0,
C1 = 1
SSTUB32866_2
Product data sheet
Rev. 02 â 9 October 2006
© NXP B.V. 2006. All rights reserved.
15 of 29
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