SAA7274 Datasheet, PDF (5/16 Pages) NXP Semiconductors – Audio Digital Input Circuit ADIC

Philips Semiconductors
Audio Digital Input Circuit (ADIC)
Product specification
SAA7274
FUNCTIONAL DESCRIPTION
Main function
The biphase input signal must conform to the IEC/EBU standards, IEC tech. com. No. 84, secr. 50, Jan. 1987 format,
as well as satisfying the following conditions:
• number of channels: 2
• transmission code: biphase mark
• synchronization method: biphase violation
• number of data bits: 24, starting with the LSB
• number of control bits: 4
• preamble values:
Table 1 Preamble values
preceding cell
block preamble
0
11101000
1
00010111
The main function performs the following tasks:
• Provides the output function with the equivalent binary value of the data bits separately for each of the two channels.
These values are available until new information is received.
• Generates an out-of-lock output signal (OLOC) which is HIGH when the frequency of the biphase input signal is equal
to 1/4 of the system clock frequency and when the block preambles are detected in the biphase input signal.
• If the biphase input signal is not present after 32 clock pulses and also whenever the biphase input signal and IOSCL/4
drift away from each other by more than 32 clock pulses, then the output OSCU is forced HIGH and output OSDU,
OPRE, OLOC, OCDB and OSDA are forced LOW.
• Generates a data clock output signal (ODCL) with a frequency of 1/4 of the system clock. When a block preamble is
detected in the biphase input signal ODCL is synchronized to a LOW value.
• Generates a word clock output signal (OWSY) with a frequency of 1/256 of the system clock. When a block preamble
is detected in the biphase input signal OWSY is synchronized to a LOW value.
• Generates a block synchronization output signal (OBSY). This signal is HIGH during 4 system clock periods and has
a frequency of 1/49152 of the system clock. The signal is synchronized with the block preambles of the biphase input
signal.
• Generates a phase output signal (OPHA) and a phase reference signal (OREF). If the frequency of the biphase input
signal (IBIFA) equals 1/4 of the system clock frequency (f_IOSCL/4) then the IC generates OPHA and OREF as shown
in Fig.3.
If the frequency of the biphase input signal (IBIFA) is greater or less than 1/4 of the system clock frequency then the
IC generates OPHA and OREF as shown in Fig.4.
July 1991
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