SA57026 Datasheet, PDF (5/8 Pages) NXP Semiconductors – 300 mA LDO with ON/OFF control and independent delayed RESET function

Philips Semiconductors
300 mA LDO with ON/OFF control and
independent delayed RESET function
Product data
SA57026
APPLICATION INFORMATION
Input capacitor
An input capacitor of ≥1 µF is required to eliminate the AC coupling
noise. This capacitor must be located as close as possible to V_IN or
GND pin (not more than 1 cm) and returned to a clean analog
ground. Any good quality ceramic, tantalum or film capacitor will
work.
Output capacitor
Phase compensation is made for securing stable operation, even if
the load current varies. For this reason, an output capacitor with
good frequency characteristics is needed. Set it as close to the
circuit as possible, with wires as short as possible.
Tha value of the output capacitance has to be at least 47 µF
connected from V_OUT to GND. When operating from sources other
than batteries, supply-noise rejection and transient response can be
improved by increasing the value of the input and output capacitors
and employing passive filtering techniques.
ON/OFF
The regulator is fully enabled when a logic HIGH is applied to this
input. The regulator enters shutdown when a logic LOW is appplied
to this input. During shutdown, regulator output voltage falls to zero,
RESET remains valid and supply current is reduced to 5 µA (typ). If
the function is not to be used, the ON/OFF pin should be tied to V_IN.
RESET output
The SA57066 has an Active-LOW RESET output. The RESET
output is driven Active-LOW within 30 µs typical (when Cd is zero
capacitance). The time delay can be adjusted up to 10 ms typical
(when Cd is 0.1 µF) of V_DET falling through the reset voltage
threshold. RESET is maintained Active-HIGH after V_DET rises above
thre reset threshold.
RESET output delay operation with an external capacitor from
Cd pin to GND
When the supply voltage crosses the release voltage (V_DET) from a
low value to a value higher than the released voltage (V_DET), the Cd
pin voltage starts to increase (charges up the external capacitor).
While the RESET output remains at LOW state condition until the
Cd pin voltage reaches the threshold operating voltage (V_OPL) 0.4 V
typical; after that, the RESET output is reversed to HIGH state
condition.
The transmission delay time (t_PLH) can be set with the capacitance
Cd of an external cpacitor as shown in Equation (1):
t_PLH + 10⁶ C
(Time is expressed in seconds; capacitance in Farads.)
Eqn. (1)
PCB layout
The component placement around the LDO should be done carefully
to achieve good dynamic line and load response. The input and
noise capacitors should be kept close to the LDO.
The rise in junction temperature depends on how efficiently the heat
is carried away from the junction to ambient. The junction to lead
thermal impedance is a characteristic of the package and fixed. The
thermal impedance between lead to ambient can be reduced by
increasing the copper area on the PCB. Increase the input, output
and ground trace area to reduce the junction-to-ambient impedance.
C
1 µF
V_IN
4
V_OUT
5
R
4.7 kΩ
2
RESET
SA57026
Cd
7
C_OUT
47 µF
3
1
6
R
C
0.1 µF
ON/OFF
Figure 3. Typical application circuit.
SL01530
2003 Oct 13
5