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| PSMN2R8-80BS Datasheet, PDF (5/14 Pages) NXP Semiconductors – N-channel 80 V, 3 m standard level FET in D2PAK | |||
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NXP Semiconductors
PSMN2R8-80BS
N-channel 80 V, 3 m⦠standard level FET in D2PAK
6. Characteristics
Table 6. Characteristics
Symbol
Parameter
Conditions
Static characteristics
V(BR)DSS
VGS(th)
drain-source
breakdown voltage
gate-source threshold
voltage
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 10
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10; see Figure 11
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
VDS = 80 V; VGS = 0 V; Tj = 25 °C
VDS = 80 V; VGS = 0 V; Tj = 175 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = 10 V; ID = 25 A; Tj = 175 °C;
see Figure 12; see Figure 13
VGS = 10 V; ID = 25 A; Tj = 100 °C;
see Figure 12; see Figure 13
VGS = 10 V; ID = 25 A; Tj = 25 °C;
see Figure 13
RG
internal gate resistance f = 1 MHz
(AC)
Dynamic characteristics
QG(tot)
QGS
QGS(th)
total gate charge
gate-source charge
pre-threshold
gate-source charge
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 75 A; VDS = 40 V; VGS = 10 V;
see Figure 14; see Figure 15
QGS(th-pl)
post-threshold
gate-source charge
QGD
VGS(pl)
gate-drain charge
gate-source plateau
voltage
ID = 75 A; VDS = 40 V;see Figure 14;
see Figure 15
Ciss
input capacitance
VDS = 40 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; see Figure 16
Crss
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
turn-off delay time
fall time
VDS = 40 V; RL = 0.53 â¦; VGS = 5 V;
RG(ext) = 10 â¦; ID = 75 A
Min Typ Max Unit
73 -
-
V
80 -
-
V
1
-
-
V
-
-
4.6 V
2
3
4
V
-
0.02 10 µA
-
-
500 µA
-
10 100 nA
-
10 100 nA
-
6.12 7.2 mâ¦
-
4.21 5
mâ¦
-
2.55 3
mâ¦
-
0.9 -
â¦
-
135 -
nC
-
139 -
nC
-
51 -
nC
-
30 -
nC
-
21 -
nC
-
27 -
nC
-
5.8 -
V
-
9961 -
pF
-
847 -
pF
-
401 -
pF
-
41 -
ns
-
43 -
ns
-
109 -
ns
-
44 -
ns
PSMN2R8-80BS
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 â 29 February 2012
© NXP B.V. 2012. All rights reserved.
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