PHW14N50E Datasheet, PDF (5/7 Pages) NXP Semiconductors – PowerMOS transistors Avalanche energy rated

Philips Semiconductors
PowerMOS transistors
Avalanche energy rated
Product specification
PHW14N50E
Gate-source voltage, VGS (V)
15
14 ID = 14A
13
12
Tj = 25 C
11
10
9
200 V
8
7
6
5
4
3
2
1
0
PHW14N50E
300 V
VDD = 400 V
0
20
40
60
80
100 120 140
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); parameter V_DS
Switching times, td(on), tr, td(off), tf (ns)
400
350
PHW14N50E
td(off)
300
250
200
150
tf
100
tr
50
td(on)
0
0
5
10
15
20
25
30
Gate Resistance, RG (Ohms)
Fig.14. Typical switching times; t_d(on), t_r, t_d(off), t_f = f(R_G)
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage;
V_(BR)DSS/V_{(BR)DSS 25 ˚C} = f(T_j)
Source-Drain Diode Current, IF (A)
20
VGS = 0 V
15
PHW14N50E
10
150 C
Tj = 25 C
5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2
Drain-Source Voltage, VSDS (V)
Fig.16. Source-Drain diode characteristic.
I_F = f(V_SDS); parameter T_j
Non-repetitive Avalanche current, IAS (A)
100
Tj prior to avalanche = 25 C
10
VDS
125 C
ID
1
1E-06
tp
PHP14N50E
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.17. Maximum permissible non-repetitive
avalanche current (I_AS) versus avalanche time (t_p);
unclamped inductive load
Maximum Repetitive Avalanche Current, IAR (A)
100
10
Tj prior to avalanche = 25 C
125 C
1
0.1
1E-06
PHP14N50E
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.18. Maximum permissible repetitive avalanche
current (I_AR) versus avalanche time (t_p)
December 1998
5
Rev 1.000