PHP45N03LT Datasheet, PDF (5/8 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP45N03LT
ID / A
60
9528-30
50
Tj / C = 25
175
40
30
20
10
0
0
1
2
3
4
5
6
VGS / V
Fig.7. Typical transfer characteristics.
I_D = f(V_GS) ; conditions: V_DS = 25 V; parameter T_j
gfs / S
25
9528-30
20
Tj / C = 25
15
175
10
5
0
0
10
20
30
40
50
60
ID / A
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D); conditions: V_DS = 25 V
a
2
30V TrenchMOS
1.5
1
0.5
0
-100
-50
0
50
100
150
200
Tj / C
Fig.9. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j); I_D = 25 A; V_GS = 5 V
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK959-60
0.5
0
-100
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2%
typ
98%
1E-04
1E-05
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
C / pF
10000
9528-30
Ciss
1000
Coss
Crss
100
0.1
1
10
100
VDS / V
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
November 1997
5
Rev 1.200