PHP45N03LT Datasheet, PDF (4/8 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP45N03LT
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
Tmb / C
Fig.1. Normalised power dissipation.
PD% = 100⋅P_D/P_{D 25 ˚C} = f(T_mb)
ID%
120
110
100
90
80
70
60
50
Normalised Current Derating
40
30
20
10
0
0
20 40 60 80 100 120 140 160 180
Tmb / C
Fig.2. Normalised continuous drain current.
ID% = 100⋅I_D/I_{D 25 ˚C} = f(T_mb); conditions: V_GS ≥ 5 V
ID / A
1000
7528-30
100
RDS(ON) ^{= VDS / ID}
10
DC
tp = 10 us
100 us
1 ms
10 ms
1
1
10
100
VDS / V
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth j-mb / (K/W)
10
D=
7528-30
1
0.5
0.2
0.1 ^0.1
0.05
0.02
P_D
tp
D=
tp
T
0
0.01
1E-07
1E-05
1E-03
t/s
T
t
1E-01
1E+01
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
ID / A
80
10
5
6
60
40
VGS / V =
9528-30
4.5
4
3.5
20
3
2.5
0
0
2
4
6
8
10
VDS / V
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
RDS(ON) / mOhm
40
30
20
10
4
VGS / V =
9528-30
4.5
5
6
10
0
0
20
40
60
80
ID / A
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
November 1997
4
Rev 1.200