PHP130N03LT Datasheet, PDF (5/6 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP130N03LT, PHB130N03LT
a
2
30V TrenchMOS
1.5
1
0.5
0
-100
-50
0
50
100
150
200
Tj / C
Fig.9. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j); I_D = 25 A; V_GS = 5 V
VGS(TO) / V
2.5
max.
2
typ.
1.5
min.
1
BUK959-60
0.5
0
-100
-50
0
50
Tj / C
100
150
200
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = V_GS
1E-01
Sub-Threshold Conduction
1E-02
1E-03
2%
typ
98%
1E-04
1E-05
1E-05
0
0.5
1
1.5
2
2.5
3
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
C / pF
10000
9506-30
Ciss
1000
Coss
Crss
100
0.1
1
10
100
VDS / V
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
VGS / V
5
9506-30
4
VDS / V = 6
24
3
2
1
0
0
20
40
60
80
100
QG / nC
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); conditions: I_D = 75 A; parameter V_DS
IF / A
100
9506-30
80
60
Tj / C = 175
25
40
20
0
0
0.5
1
1.5
2
VSDS / V
Fig.14. Typical reverse diode current.
I_F = f(V_SDS); conditions: V_GS = 0 V; parameter T_j
January 1998
5
Rev 1.300