PHP130N03LT Datasheet, PDF (4/6 Pages) NXP Semiconductors – TrenchMOS transistor Logic level FET

Philips Semiconductors
TrenchMOS™ transistor
Logic level FET
Product specification
PHP130N03LT, PHB130N03LT
1000 ^{Drain current, ID (A)}
100 ^{RDS(ON) = VDS / ID}
DC
10
7506-30
tp = 10 us
100 us
1 ms
10 ms
100 ms
1
1
10
100
Drain-source voltage, VDS (V)
Fig.3. Safe operating area. T_mb = 25 ˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Zth / (K/W)
1E+00
0.5
1E-01
0.2
0.1
0.05
1E-02 ^0.02
P_D
tp
D
=
tp
T
0
T
t
1E-03
1E-07
1E-05
1E-03
t/s
1E-01
1E+01
Fig.4. Transient thermal impedance.
Z_{th j-mb} = f(t); parameter D = t_p/T
ID / A
100
6 3.5
5
80
60
BUK9506-30
3
VGS / V =
2.8
40
2.6
20
2.4
2.2
0
0
2
4
6
8
10
VDS / V
Fig.5. Typical output characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_GS
RDS(ON) / mOhm
10
3
8
6
4
9506-30
3.5
4
5
6
2
0
0
20
40
60
80
100
ID / A
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(I_D); parameter V_GS
ID / A
100
9506-30
80
60
Tj / C = 175
25
40
20
0
0
1
2
3
4
5
VGS / V
Fig.7. Typical transfer characteristics.
I_D = f(V_GS) ; conditions: V_DS = 25 V; parameter T_j
gfs / S
100
9506-30
80
Tj / C = 25
60
175
40
20
0
0
20
40
60
80
100
ID / A
Fig.8. Typical transconductance, T_j = 25 ˚C.
g_fs = f(I_D); conditions: V_DS = 25 V
January 1998
4
Rev 1.300