IRF840 Datasheet, PDF (5/7 Pages) Motorola, Inc – N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR

Philips Semiconductors
PowerMOS transistor
Avalanche energy rated
Product specification
IRF840
Gate-source voltage, VGS (V)
15
14 ID = 8.5A
13
12
Tj = 25 C
11
10
100V
9
8
7
6
5
4
3
2
1
0
200V
PHP8N50E
VDD = 400 V
0
20
40
60
80
Gate charge, QG (nC)
Fig.13. Typical turn-on gate-charge characteristics.
V_GS = f(Q_G); parameter V_DS
Switching times (ns)
1000
VDD = 250 V
VGS = 10 V
RD = 30 Ohms
Tj = 25 C
PHP8N50
100 ^td(off)
tf
tr
td(on)
10
0
10
20
30
40
50
60
RG, Gate resistance (Ohms)
Fig.14. Typical switching times; t_d(on), t_r, t_d(off), t_f = f(R_G)
Normalised Drain-source breakdown voltage
1.15
V(BR)DSS @ Tj
V(BR)DSS @ 25 C
1.1
1.05
1
0.95
0.9
0.85
-100
-50
0
50
100
150
Tj, Junction temperature (C)
Fig.15. Normalised drain-source breakdown voltage;
V_(BR)DSS/V_{(BR)DSS 25 ˚C} = f(T_j)
20 ^{IF, Source-Drain diode current (Amps)}
VGS = 0 V
15
PHP8N50
10
150 C
Tj = 25 C
5
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4
VSDS, Source-Drain voltage (Volts)
Fig.16. Source-Drain diode characteristic.
I_F = f(V_SDS); parameter T_j
Non-repetitive Avalanche current, IAS (A)
10
25 C
Tj prior to avalanche = 125 C
1
VDS
ID
0.1
1E-06
tp
PHP8N50E
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.17. Maximum permissible non-repetitive
avalanche current (I_AS) versus avalanche time (t_p);
unclamped inductive load
Maximum Repetitive Avalanche Current, IAR (A)
10
Tj prior to avalanche = 25 C
1
125 C
0.1
0.01
1E-06
PHP8N50E
1E-05
1E-04
1E-03
Avalanche time, tp (s)
1E-02
Fig.18. Maximum permissible repetitive avalanche
current (I_AR) versus avalanche time (t_p)
March 1999
5
Rev 1.000