IRF840 Datasheet, PDF (4/7 Pages) Motorola, Inc – N-CHANNEL ENHANCEMENT-MODE SILICON GATE TMOS POWER FIELD EFFECT TRANSISTOR

Philips Semiconductors
PowerMOS transistor
Avalanche energy rated
25 ^{ID, Drain current (Amps)}
VDS > ID x RDS(on)max
20
PHP8N50
15
10
5
Tj = 150 C
Tj = 25 C
0
0
2
4
6
8
10
VGS, Gate-Source voltage (Volts)
Fig.7. Typical transfer characteristics.
I_D = f(V_GS); parameter T_j
gfs, Transconductance (S)
10
VDS > ID x RDS(on)max
Tj = 25 C
8
6
PHP8N50
150 C
4
2
0
0
5
10
15
20
25
ID, Drain current (A)
Fig.8. Typical transconductance.
g_fs = f(I_D); parameter T_j
a
2
Normalised RDS(ON) = f(Tj)
1
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.9. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_{DS(ON)25 ˚C} = f(T_j); I_D = 4.25 A; V_GS = 10 V
Product specification
IRF840
VGS(TO) / V
4
3
2
max.
typ.
min.
1
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.10. Gate threshold voltage.
V_GS(TO) = f(T_j); conditions: I_D = 0.25 mA; V_DS = V_GS
1E-01 ^{ID / A}
SUB-THRESHOLD CONDUCTION
1E-02
1E-03
2%
typ
98 %
1E-04
1E-05
1E-06
0
1
2
3
4
VGS / V
Fig.11. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C; V_DS = V_GS
10000 ^{Junction capacitances (pF)}
PHP8N50
Ciss
1000
100
Coss
Crss
10
1
10
100
VDS, Drain-Source voltage (Volts)
1000
Fig.12. Typical capacitances, C_iss, C_oss, C_rss.
C = f(V_DS); conditions: V_GS = 0 V; f = 1 MHz
March 1999
4
Rev 1.000