BUK107-50DL Datasheet, PDF (5/9 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK107-50DL
200 ^{Tj(TO) / C}
BUK107-50DL
180
160
140
TYP.
120
100
80
60
0
2
4
6
8
10
VIS / V
Fig.8. Typical overtemperature protection threshold.
T_j(TO) = f(V_IS); condition: V_DS = 10 V
IIS & IISL / mA
1.0
BUK107-50DL
0.9
0.8
0.7
LATCHED
0.6
0.5
0.4
0.3
RESET
0.2
NORMAL
IISL
IIS
0.1
0
0
2
4
6
8
VIS / V
Fig.9. Typical DC input characteristics, T_j = 25 ˚C.
I_IS & I_ISL = f(V_IS); normal operation & protection latched
IIS / uA
500
400
300
VIS / V =
5V
BUK107-50DL
200
4V
100
0
-50
0
50
100
150
Tj / C
Fig.10. Typical DC input current.
I_IS = f(T_j); parameter V_IS; normal operation
VIS(TO) / V
3
2
1
BUK107-50DL
MAX.
TYP.
MIN.
-50
0
50
100
150
Tj / C
Fig.11. Input threshold voltage.
V_IS(TO) = f(T_j); conditions: I_D = 1 mA; V_DS = 5 V
II / mA
10
BUK107-50DL
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
VIS / V
Fig.12. Typical input clamping characteristic.
I_I = f(V_IS); normal operation, T_j = 25 ˚C.
ID / mA
200
BUK107-50DL
150
TYP.
100
50
0
50
52
54
56
58
60
VDS / V
Fig.13. Overvoltage clamping characteristic, 25 ˚C.
I_D = f(V_DS); conditions: V_IS = 0 V; t_p ≤ 300 µs
March 1997
5
Rev 1.200