BUK107-50DL Datasheet, PDF (4/9 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET

Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK107-50DL
120 ^PD%
Normalised Power Derating
110
100
90
80
70
60
50
40
30
20
10
0
0 20 40 60 80 100 120 140
Tmb / C
Fig.2. Normalised limiting power dissipation.
P_D% = 100⋅P_D/P_D(25 ˚C) = f(T_mb)
ID / A
2.0
1.5
BUK107-50DL
CURRENT LIMITING OCCURS
WITHIN THE SHADED REGION
1.0
TYP.
0.5
0
0
20
40
60
80 100 120 140
Tamb / C
Fig.3. Continuous drain current.
I_D = f(T_amb); condition: V_IS = 5 V
ID / A
1.5
1
0.5
BUK107-50DL
VIS / V =
7
6
5
4
0
0
4
8
12 16 20 24 28 32
VDS / V
Fig.4. Typical on-state characteristics, T_j = 25 ˚C.
I_D = f(V_DS); parameter V_IS; t_p = 300 µs
a
1.5
Normalised RDS(ON) = f(Tj)
1.0
0.5
0
-60 -40 -20 0 20 40 60 80 100 120 140
Tj / C
Fig.5. Normalised drain-source on-state resistance.
a = R_DS(ON)/R_DS(ON)25 ˚C = f(T_j); I_D = 100 mA; V_IS = 5 V
RDS(ON) / mOhm
240
200
MAX.
BUK107-50DL
160
TYP.
120
80
40
0
0
2
4
6
8
10
VIS / V
Fig.6. Typical on-state resistance, T_j = 25 ˚C.
R_DS(ON) = f(V_IS); conditions: I_D = 100 mA, t_p = 300 µs
ID / A
1.5
BUK107-50DL
1
0.5
0
0
2
4
6
8
10
VIS / V
Fig.7. Typical transfer characteristics, T_j = 25 ˚C.
I_D = f(V_IS); conditions: V_DS = 10 V, t_p = 300 µs
March 1997
4
Rev 1.200