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BUK107-50DL Datasheet, PDF (3/9 Pages) NXP Semiconductors – PowerMOS transistor Logic level TOPFET
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK107-50DL
THERMAL CHARACTERISTICS
SYMBOL PARAMETER
Rth j-sp
Rth j-b
Rth j-a
Thermal resistance
Junction to solder point
Junction to board1
Junction to ambient
CONDITIONS
Mounted on any PCB
Mounted on PCB of fig. 19
MIN. TYP. MAX. UNIT
-
12 18 K/W
-
40
- K/W
-
-
70 K/W
STATIC CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
V(CL)DSS
V(CL)DSS
Drain-source clamping voltage
Drain-source clamping voltage
IDSS
IDSS
IDSS
RDS(ON)
Off-state drain current
Off-state drain current
Off-state drain current
Drain-source on-state
resistance2
CONDITIONS
VIS = 0 V; ID = 10 mA
VIS = 0 V; IDM = 200 mA;
tp ≤ 300 µs; δ ≤ 0.01
VDS = 45 V; VIS = 0 V
VDS = 50 V; VIS = 0 V
VDS = 40 V; VIS = 0 V; Tj = 100 ˚C
VIS = 5 V; IDM = 100 mA;
tp ≤ 300 µs; δ ≤ 0.01
MIN.
50
-
TYP.
55
56
MAX.
-
70
UNIT
V
V
-
0.5
2
µA
-
1
20 µA
-
10 100 µA
-
150 200 mΩ
INPUT CHARACTERISTICS
Tb = 25 ˚C unless otherwise specified. The supply for the logic and overload protection is taken from the input.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
VIS(TO)
IIS
IISL
VISR
V(CL)IS
RIG
Input threshold voltage
VDS = 5 V; ID = 1 mA
1.7 2.2 2.7 V
Input supply current
normal operation;
VIS = 5 V
-
330 450 µA
VIS = 4 V
-
170 270 µA
Input supply current
protection latched;
VIS = 5 V
-
500 650 µA
VIS = 3.5 V
-
250 400 µA
Protection latch reset voltage3
1
2.2 3.5
V
Input clamping voltage
Input series resistance
II = 1.5 mA
to gate of power MOSFET
6
7.5
-
V
-
33
-
kΩ
SWITCHING CHARACTERISTICS
Tamb = 25 ˚C; resistive load RL = 50 Ω; adjust VDD to obtain ID = 250 mA; refer to test circuit and waveforms
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
td on
Turn-on delay time
tr
Rise time
td off
Turn-off delay time
tf
Fall time
VIS = 0 V to VIS = 5 V
VIS = 5 V to VIS = 0 V
-
8
-
µs
-
30
-
µs
-
3
-
µs
-
6
-
µs
1 Temperature measured 1.3 mm from tab.
2 Continuous input voltage. The specified pulse width is for the drain current.
3 The input voltage below which the overload protection circuits will be reset.
March 1997
3
Rev 1.200
 ▷