74VHC_VHCT595_15 Datasheet, PDF (5/22 Pages) NXP Semiconductors – 8-bit serial-in/serial-out or parallel-out shift register with output latches

NXP Semiconductors
74VHC595; 74VHCT595
8-bit serial-in/serial-out or parallel-out shift register with output latches
7. Functional description
Table 3. Function table^[1]
Control
SHCP STCP OE MR
X
X
L
L
X

L
L
X
X
H
L

X
L
H
X

L
H


L
H
Input Output
DS Q7S Qn
X
L
NC
X
L
L
X
L
Z
H
Q6S NC
X
NC QnS
X
Q6S QnS
Function
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1] H = HIGH voltage state;
L = LOW voltage state;
 = LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
DS
STCP
MR
OE
Q0
Q1
Q6
Q7
Q7S
Z-state
Z-state
Z-state
Z-state
Fig 7. Timing diagram
74VHC_VHCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2012
© NXP B.V. 2012. All rights reserved.
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