74F5074 Datasheet, PDF (5/12 Pages) NXP Semiconductors – Synchronizing dual D-type flip-flop/clock driver

Philips Semiconductors
Synchronizing dual D-type flip-flop/clock driver
Product specification
74F5074
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
10⁶ 10⁸
10¹⁰ 10¹²
10¹²
10¹¹
10,000 years
10¹⁰
MTBF in seconds
100 years ₁₀₉
10⁸
one year
10⁷
10¹⁴
10¹⁵ = f_Cf_I
10⁶
one week
7
8
9
10
t’ in nanoseconds
NOTE: V_CC = 5V, T_amb = 25°C, τ =135ps, To = 9.8 X 10⁶ sec
Figure 4.
SF00589
TYPICAL VALUES FOR τ AND T₀ AT VARIOUS V_CCS AND TEMPERATURES
T_amb = 0°C
T_amb = 25°C
V_CC
5.5V
τ
125ps
T₀
1.0 X 10⁹ sec
τ
138ps
T₀
5.4 X 10⁶ sec
5.0V
115ps
1.3 X 10¹⁰ sec
135ps
9.8 X 10⁶ sec
4.5V
115ps
3.4 X 10¹³ sec
132ps
5.1 X 10⁸ sec
τ
160ps
167ps
175ps
T_amb = 70°C
T₀
1.7 X 10⁵ sec
3.9 X 10⁴ sec
7.3 X 10⁴ sec
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
SD
RD
CP
D
Q
Q
MODE
L
H
X
X
H
L
Asynchronous set
H
L
X
X
L
H
Asynchronous reset
L
L
X
X
H
H
Undetermined*
H
H
↑
h
H
L
Load “1”
H
H
↑
l
L
H
Load “0”
H
H
↑
X
NC
NC
Hold
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low–to–high clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low–to–high clock transition
NC= No change from the previous setup
X = Don’t care
↑ = Low–to–high clock transition
↑ = Not low–to–high clock transition
* = This setup is unstable and will change when either set or reset return to the high level
September 14, 1990
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